Can we have write data before address in AXI?

UVM
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To have a write data before write address in AXI, master will be sending WVALID & WDATA before driving AWVALID. I found some content online which says Data before address is possible if write address channel contains more register stages than the write data channel, what does it mean? Can anyone explain how we can achieve this feature?

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In reply to S_Kadam:

You might want to discuss this in an ARM community forum

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In reply to dave_59:

Okay, thank you Sir.