Hello everyone, I’m a senior in EE at Purdue, currently working on AXI UVM. While there are some resources available, does anyone know of a good guide on verifying a bus protocol? I’d really appreciate any help ASAP, as I’m in Senior Design and this is my last semester. My current plan is to verify the AXI master using a BUS model. Here are some questions I have:
- This is more of an explanation then a question but the reason we are using bus models is because I have a partner on this project who is verifying the AXI slave. Is this is a good approach to verify the AXI protocol? I really want this project to work out so I get better at UVM and am able to hopefully end up with a Job in UVM someday.
- Since I am using a bus model to verify the master should I connect my sequencer to my scoreboard and once the monitor sends the output of the DUT from the scoreboard just compare the 2 then?
- Any major issues I am overlooking with the approach/Advice that may help me?
Below is what I was thinking
