How does AXI/AHB protocols avoid race conditions

SystemVerilog
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1

I wanted to know if there is any way that RACE condition is avoided in AXI or AHB protocol.
If yes, is it with the help of LOCKED accesses or EXCLUSIVE accesses?

2

In reply to Ammu89:

By saying race you mean read and write to the same address at the same time?

If yes
I think this is not the responsibility of the bus to handle that.