Topic	Replies	Views	Activity
While doing uvm_reg_hw_reset_seq getting error stating value read from DUT does not match mirrored value UVM UVM , Systemverilog-UVM-RAL , RAL-UVM , model-uvm-reference_model	2	253	January 10, 2024
UVM Framework for Timer Peripheral UVM UVM , model-uvm-reference_model	1	199	November 29, 2023
How to design a robust scoreboard? UVM UVM , scoreboard , Golden-Model , model-uvm-reference_model	2	263	November 15, 2023
I am trying to understand the way I can write a UVM scoreboard for a DUT(arbiter) with multiple masters and one slave like 3 AXI masters-> DUT-> AXI slave UVM SystemVerilog , UVM , AMBA-AXI , AMBA-VIP , model-uvm-reference_model , coverage-UVM-module-class	3	344	August 24, 2023
How to write UVM driver and sequence item for a vending machine design (interview question)? UVM SystemVerilog , UVM , model-uvm-reference_model	0	239	August 7, 2023
How to use register inside the DUT in scoreboard UVM UVM , uvm-scorebaord , DMA , model-uvm-reference_model	2	395	May 5, 2023
In AXI, at what scenario can use out of order and outstanding transactions SystemVerilog SystemVerilog , AMBA-AXI , model-uvm-reference_model	2	1999	July 20, 2022
Is ther any method to generate and drive 1bit serial complex input stimulus? UVM UVM , uvm-uvm_driver- , package-variable-uvm , model-uvm-reference_model	1	485	November 8, 2021
How can I drive complex input in DUT? UVM UVM , uvm-uvm_driver- , model-uvm-reference_model	4	563	November 6, 2021

model-uvm-reference_model