While doing uvm_reg_hw_reset_seq getting error stating value read from DUT does not match mirrored value

While doing RAL default test: uvm_reg_hw_reset_seq getting an UVM_ERROR: reporter [RegModel] Register “mc_regmodel.DD_Controller.D_CTL_0000” value read from DUT (0x0000000000000000) does not match mirrored value (0x0000000010460000).

In reply to newbie_342:

The UVM_ERROR you’re encountering indicates a mismatch between the value read from the DUT for a specific register and the mirrored value in the RAL (Register Abstraction Layer). This type of error typically occurs during the verification process when a sequence or test attempts to verify the correctness of register values.

Here are some steps you can take to investigate and resolve this issue:

Check the Mirrored Value:
Examine the mirrored value of the register mc_regmodel.DD_Controller.D_CTL_0000 in your RAL model. This is the expected value that the read value from the DUT should match.
Inspect the mirrored value using the read() method or directly accessing the default field in the RAL.

Verify the DUT Value:
Check the actual value read from the DUT for the register in question. This can be done using the read() method or equivalent in your testbench code.
Ensure that the value read from the DUT matches the expected mirrored value. If not, there might be an issue with the DUT or the register read logic.

Check for Register Reset:
Verify if the register D_CTL_0000 is expected to have a default value after a reset. The mirrored value is typically set to the default value during the reset phase.
If the mirrored value is correct, ensure that your reset sequence is properly configured and executed.

Inspect Register Configuration:
Confirm that the configuration parameters of the register D_CTL_0000 are set correctly. This includes fields such as width, access type, etc.
Ensure that the mirrored value is computed correctly based on the register configuration.

Check for Write Sequences:
If your test involves write sequences to the register, ensure that these sequences are correct and executed in the expected order.
Confirm that any modifications to the register’s value are correctly mirrored in the RAL.

Debug with Print Statements:
Insert print statements or debug messages in your sequences and RAL code to trace the values at different stages of the test.

Review RAL Configuration:
Double-check the RAL configuration and ensure that the register model hierarchy matches the actual design hierarchy.

Review Sequences:
Inspect the sequences used in your test and verify that they correctly model the expected behavior of the design.

By systematically checking these aspects, you should be able to identify the root cause of the mismatch between the DUT register value and the mirrored value in the RAL. If the issue persists, you may need to provide more details about your RAL configuration, register model, and relevant parts of your testbench code for a more specific diagnosis.

Freelancer/verification engineer

Thanks @rahulvala for the detailed information.
But It seems everything is good ,but still i can see read data as “0” only. can you please tell what might be the issue and how to debug it.

Thanks & Regards,