I was asked this question in a DV interview and I am curious to know what I missed or what can be a better way to do it . Please lend your suggestions.

Question:

I need to write pseudocode for seq item, driver and tell scenarios which I will check for verifying the following design:

A vending machine which has following :

- inputs → amount, valid, done
- outputs → soda_out, change

A soda costs $60. Amount can be 1, 2, 5 or 10 in dollars. Every time a currency is inserted, `valid`

is high for the next cycle and once all currencies for the are inserted, `done`

goes high for one cycle and `soda_out`

output goes 1 if total is $60 and change comes out if its more that $60.

Here is what I wrote:

```
class vending_pkt extends uvm_sequence_item;
typedef enum {1,2,3,10} currency ;
rand currency amount[];
randc currency value;
int change;
bit soda_out;
constraint c1 {amount.sum() >=60 ;}
// to check if all all currencies inserted are same, i will turn this constraint on only for one seq
constraint c2 { foreach(amount[i])
amount[i]==value;
}
//to check if all type currencies are inserted, will turn this constraint on only for one seq
constraint c3 {
amount.sum() with (int'(item == 1))>0;
amount.sum() with (int'(item == 2))>0;
amount.sum() with (int'(item == 5))>0;
amount.sum() with (int'(item == 10))>0;
}
endclass
```

**DRIVER RUN_PHASE :

**

virtual task run_phase(uvm_phase phase)

```
seq_item_port.get_next_item(req);
drive(req);
seq_item_port.item_done()
virtual task drive(vending_pkt req)
int i=0;
repeat(req.amount.size())
begin
vif.cb.amount<=req.amount[i]
@(posedge vif.cb)
vif.cb.valid<=1'b1;
@(posedge clk)
i++;
end
vif.cb.done<=1'b1;
endtask
endtask
```

For the scenarios, I thought of checking if same kind of currencies are inserted, all different currencies are inserted or random, if sum is exact $60, if sum is $59, sum is $61.Please let me know your thoughts or test scenarios you can think of as DV person.