UVM Framework for Timer Peripheral

Hello, can anyone assist me in creating a golden model for a timer? This model should be able to compare the count of the RTL (Register-Transfer Level) and the Golden Model in various modes, including free-running mode and periodic mode.

In reply to ARK010:

Creating a golden model in Verilog involves writing a software simulation of the expected behavior of your hardware design. Here’s a basic example for a timer in Verilog:

module TimerGoldenModel;

  // Parameters
  parameter FREE_RUNNING = 2'b00;
  parameter PERIODIC = 2'b01;

  // Inputs
  input wire clk;
  input wire rst_n;
  input wire mode;
  input wire [31:0] period;

  // Outputs
  output wire [31:0] count;

  // Internal registers
  reg [31:0] internal_count;

  always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
      internal_count <= 0;
    end else begin
        FREE_RUNNING: internal_count <= internal_count + 1;
        PERIODIC: begin
          if (internal_count == period - 1) begin
            internal_count <= 0;
          end else begin
            internal_count <= internal_count + 1;
        default: internal_count <= internal_count; // No change

  assign count = internal_count;


In this example, I’ve implemented a simple timer in Verilog with a count output. The timer has two modes: FREE_RUNNING and PERIODIC. The internal_count register is incremented based on the selected mode. The period input is used in PERIODIC mode to reset the count after a specified period.

You can instantiate this TimerGoldenModel module in your testbench and simulate it alongside your RTL design. In your testbench, you can then compare the output of your RTL design with the expected behavior modeled by this golden model.

Freelancer/verification engineer