I am trying to understand the way I can write a UVM scoreboard for a DUT(arbiter) with multiple masters and one slave like 3 AXI masters-> DUT-> AXI slave

UVM
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I need to write a scoreboard for a DUT which has 3 AXI masters as input and one of them goes out on the other side to AXI slave…like 3 AXI masters-> DUT-> AXI slave. Please let me know if my understanding below is correct or are there any more ways to do it.

Since there are three AXI master interfaces and one goes out to the slave, i will need to instantiate the interface 4 times–> like axi_interface m1,m2,m3,m_out, am I correct ?

My scoreboard will get AXI transactions from one monitor which I can add in the env which will be sampling AXI transaction 1 (m_tran_1), AXI transaction 2(m_tran_2) and AXI transaction 3 (m_tran_3) from 3 instantiations of AXI master interface .In this monitor, I can wait for req1,req2 or req3 to go high and and based on round robin (for example ), it will make gnt_1, gnt_2 or gnt_3 high and send that transaction to the sb which will store it in a queue say expected_q, and sb will also get AXI output transaction (m_out_trans) from this monitor and stores as actual_q and compares both expected_q and actual_q transactions ?

Is my understanding correct ?
Is it okay to add a monitor in the env to get hold of all the 3 master transactions ?
Is there a better way of doing it ?

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In reply to GC:

In yo3masters and 1 lave are connected to this busur case my understanding is different. You have 1 AXI bus interface.

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In reply to chr_sue:

I have 3 axi masters connected to the arbiter/DUT and one of the master buses allowed to go out.
I have never worked on a multi master scenario, just want to understand how does it work and if my understanding is correct ?

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In reply to GC:

Looked like my last answer was hacked.
Again, you have 3 masters connected to the same bus and also the slave(s) are connected to the same bus. You have to take care only 1 master is active at a certain time. In the other case you get a bus contention resulting in x’s on your bus.
After having 1 msater acitve a slave responds to the master request.