Are you a Design or Verification Engineer or Manager interested in UVM & SystemVerilog?
Join principal instructor, Chris Spear as he presents UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know.
Overview:
Learn how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs. These strategies are based on decades of experience with functional verification in Verilog, SystemVerilog, and verification methodologies including UVM, OVM, VMM, and more.
What You Will Learn:
- High performance method to distribute configuration information throughout a testbench
- A simple Object Oriented Programming method that is more robust and easier to use than the UVM configuration database (uvm_config_db)
- Do’s and don’ts on creating UVM sequence item classes to describe your transactions
- A simple approach to starting sequences of transactions, and sharing configuration information
- Creating methods to provide a high-level interface to sequences
- Tradeoffs between the uvm_do macros and their atomic operations
- Improving simulation performance with phase objection alternatives
- UVM factory introduction
- The best way to perform and check SystemVerilog randomization
- A common Verilog expression gotcha that trips even experienced coders
Now available to view or download. |