Intigrating VIP in SOC environment

UVM
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1

Hi,
I have SPI VIP in SV/UVM Environment. which is having testcase and sequences for checking all functionality of SPI IP. I have ARM processor (Cortex M3) based SOC in this I am having SPI module to be verified.

Can any body explain how we can use this VIP to verify SPI in SOC level? I mean how we can integrate it to SOC testbench?
After integration can be use same sequences to verify?
Only BFM integration will be enough to verify it or we can integrate with all verification component?
Can we use uvm test/SV test in SOC to verify if yes then how? or only C and ASM test we can have for verification in ARM based SOC?
If any body can answer these few question will be great full of him/her.

Regards,
Amit Soni

2

Can any body explain how we can use this VIP to verify SPI in SOC level? I mean how we can integrate it to SOC testbench?
– if VIP is from third party then you can contact them for integration or it is developed by you then you can treat it as agent and add it in your environment and make necessary connections.

After integration can be use same sequences to verify?
– it depends,if you want hit only few scenarios then those sequences are enough or else you need to write more sequences

Only BFM integration will be enough to verify it or we can integrate with all verification component?
– again it depends on how you want verify your Design,if want to do coverage,score-boarding,monitoring then all other components are required

Can we use uvm test/SV test in SOC to verify if yes then how? or only C and ASM test we can have for verification in ARM based SOC?
– yes, you can use uvm test/SV test.
generally processor will start execution by reading the hex code from memory,so you can load the hex code into memory by reading the .hex file in your uvm test/SV test.