Verification Academy

post-synthesis-verification

Topic		Replies	Views	Activity
Post Synthesis Simulation error, unable to find ports due to flattening 2D array ports to 1D SystemVerilog SystemVerilog , System-Verilog , post-synthesis-verification		2	419	August 23, 2023
SystemVerilog assertions in synthesized design SystemVerilog SystemVerilog , functional-verification , SVA-Assertion , post-synthesis-verification		4	4691	January 8, 2021