In post synthesis simulation on Vivado, the netlist flattens 2D array to 1D array. How can we adapt the test-bench to the change of these ports (for example in DUT instantiation, feeding values to this port through $fscanf function))
Example: reg signed [13-1:0] mac_ofdIsymbol_tqs [1:0];
this port is now flattened in the netlist to mac_ofdIsymbol_tqs[0][12:0] and mac_ofdIsymbol_tqs[1][12:0]
In reply to Farah_Adel_Fathy:
You need to show exactly how the ports are declared. When you sat flattened, do you mean split into separate ports for each unpacked element?
In reply to dave_59:
It is now solved. I defined a wrapper that has the instantiation of this module (that has the 2D array ports). This wrapper maps the 1D array ports to 2D and passes it to the targeted module
Illustration: The wrapper has these signals defined:
input signed [13-1:0] mac_ofdIsymbol_tqs_0,
wire signed [13-1:0] mac_ofdIsymbol_tqs [1:0];
assign mac_ofdIsymbol_tqs [0] = mac_ofdIsymbol_tqs_0;
assign mac_ofdIsymbol_tqs [1] = mac_ofdIsymbol_tqs_1;
And mac_ofdIsymbol_tqs enters the required module (which is instantiated now under wrapper). As long as 2D arrays are not in the interface there will be no issue.