In reply to jvkodali:
If you are asking whether it matters whether you use Verilog or VHDL for RTL design when you are using SystemVerilog/UVM for verification, I would say use the language that you have the resources to support. IMHO, it think it would be better if everyone used SystemVerilog for both design and verification. That way it is easier to shift resources between design and verification. However, there are some people that believe it is best for verification if verification engineers did not understand how to read RTL code. I don’t agree with that.