If you are asking specifically about verification, and not design, then we will suggest that you make the comparison with SystemVerilog versus VHDL or Verilog. Developing a verification test is a software programming task, not a design task. SystemVerilog was developed to merge the two worlds together in a single language, plus added features specifically for functional coverage and constrained random test generation. The UVM base class library and methodology is the established standard for writing verification testbenches, and that gives you access to a plethora of standard methodology guidelines, training, and Verification IP.