In reply to jvkodali:
I was asked to prepare a presentation on the topic below for a job interview:
Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
That’s a good interview question because it demonstrates how much you really know about design and verification. It is also a tricky question because it can also show the weaknesses in your understanding of the whole verification problems. Thus, you need to address the process of verification, including:
- requirements: How defined
- verification plan: What’s in it, what to test
- verification architecture and methodologies
- Use of assertions
- Use of constrained-random tests
- Use of coverage (functional being of importance here)
- Maybe formal verification?
- Use of UVM (maybe)
- Languages
- Limits of VHDL for verification
- Features of SystemVerilog supporting verification
I authored several books on VHDL and Verilog (which represents the RTL part of SystemVerilog) and to me, the two languages are pretty much similar, except for syntax. After being a very strong advocate of VHDL, I changed my beliefs and switched to SystemVerilog, even for just the Verilog subset of it. It is less restrictive, but requires good coding guidelines. I am also a very strong advocate of SystemVerilog assertions (SVA) because they help in the clarification of the requirements and in the debugging and verification process. Formal verification is gaining wide acceptance, and uses SVA for the definitions of the properties of the design. I also like the UVM methodology and approaches, though UVM is not very straightforward, and requires care, with a good understanding of SystemVerilog. However, with some guidance and rules, I believe that one can effectively use UVM with a lesser than full
understanding of SystemVerilog. What I am talking about it is the use of predefined templates for the basic building blocks.
Best wishes in your endeavors, and show a good understanding of the whole verification issues; the languages are just vehicles to achieve those goals, and though important, they are not the whole solution.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115