Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification

SystemVerilog
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In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for your insight. I understand that a lot depends on the Verification methodology.

Are there any language specific features that help in Verification. I would appreciate any information contrasting Verilog, VHDL and System Verilog for Verification.

Because of various opinions and no clear resourses on Web on this particualar topic, I am finding it difficult. All comparisions are in general talking about the general features.

I came accross one of your thread from 2000.

http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=66

I look forward to hearing from you soon.