In reply to jvkodali:
If you are only talking about the verification domain, then the comparison needs to be between VHDL and SystemVerilog, not Verilog. SystemVerilog has all the dynamic software programming features that you need to create a testbench, and the object-oriented programming features to make that testbench reusable. And then there are are the testbench specific features that I mentioned at the beginning of my response. But you can’t just look at the technical features. There is the cost of getting people trained, especially if you have only VHDL expertise in-house. And then you have to look at the available verification IP that you may need in case you do not have the resources available to write it yourself (How much time to you want to spend verifying your testbench instead of your DUT?). That’s where SystemVerilog along with standard UVM based verification IP can help you tremendously.