Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification

SystemVerilog
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In reply to jvkodali:

Are there any language specific features that help in Verification.

SV supports specific features for verifcation, and those are not supported by VHDL.
Several aspects are needed in verif:

  1. Stimulus generator. For that SV supports:
    a) Constraint random generation with random gen stability.
    FYI, on rnd stability: This explains it: WWW.TESTBENCH.IN - Systemverilog Randomization
    Basically, this deals with reproducability because of calls to RNG (random number generator_.
    in Verilog, there is 1 RNG with the $random(), thus if you make changes to modules (or threads) that call the RNG (e.g., module x adds one more RNG in this new model) you would not get the same random numbers as the previous run.

In SystemVerilog seeding will be done hierachily. Every module instance, interface instance, program instance and package has initialization RNG. Every thread and object has independent RNG . When ever dynamic thread is created its RNG is initialized with the next random value from its parent thread. RNG initialization and RNG generation are different process (see the link for more info). But that works with the ​$urandom,$urandom_range, or std::randomize()

Thus, in a nutshell, the $random is verilog thingy, whereas ​$urandom,$urandom_range, or std::randomize() are SV where each thread has its own RNG; if one thread adds another RNG call, it does not disturb the other RNGs in the other threads.

  1. Verification of results:
    This is supported by SVA and by dta structures needed for verif. Am thinking of stuff like associative arrays, queus, mailboxes, the generate statement (like VHDL), vectors.

  2. Coverage to determine when done, or how much was done.
    SV has the cSVA cover and the covergroup to help in that respect.

  3. flexibility for changes
    SV has classes that can be extended and dynamically linked to other classes to accommodate changes and tests.

  4. standards: UVM was developed to facilitate the standardization for the development of TBs.

On Verilog, as Dave mentioned, it is a subset of SV, and more at the RTL level. Not very useful for the verif of large designs.
On VHDL, it lacks the above aspects.
Ben Cohen systemverilog.us