DUT
Topic | Replies | Views | Activity | |
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How to access a DUT signal from a UVM test case class? | 21 | 39111 | April 11, 2023 | |
Driving DUT internal signals with bind module | 2 | 1830 | October 24, 2020 | |
Connection between DUT and TB without Interface | 3 | 1607 | February 22, 2020 | |
How to write structural Logic in Class | 2 | 1129 | July 31, 2018 | |
VIP design | 9 | 1973 | July 24, 2018 | |
Verification of dut.how to acess | 5 | 1614 | June 29, 2016 |