DUT
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| How to access a DUT signal from a UVM test case class? |
|
21 | 39577 | April 11, 2023 |
| Driving DUT internal signals with bind module |
|
2 | 1997 | October 24, 2020 |
| Connection between DUT and TB without Interface |
|
3 | 1652 | February 22, 2020 |
| How to write structural Logic in Class |
|
2 | 1139 | July 31, 2018 |
| VIP design |
|
9 | 2035 | July 24, 2018 |
| Verification of dut.how to acess |
|
5 | 1633 | June 29, 2016 |