Topics tagged interface

Topic	Replies	Views	Activity
Parameter type in interface SystemVerilog SystemVerilog , interface	1	36	April 16, 2024
"Undefined module: <interface> was used. Port connection rules will not be checked at such instantiations." UVM SystemVerilog , UVM , configuration , virtual-interface , interface	2	45	March 27, 2024
Task arguments behaviour in SV interface SystemVerilog SystemVerilog , interface	5	87	February 28, 2024
Assign parameter in interface SystemVerilog parameter , interface	5	83	February 18, 2024
Error during testbench to dut connection using asbtract class + interfaces SystemVerilog interface , Abstract-class , pure-virtual-methods	4	108	December 29, 2023
Interface modport: one signal always connected to a default value SystemVerilog SystemVerilog , interface , SystemVerilog-modport	5	275	November 29, 2023
Interface direct connection at top level SystemVerilog SystemVerilog , interface	1	176	October 5, 2023
Interface BFM and port direction SystemVerilog SystemVerilog , interface , clockingblock	1	202	September 23, 2023
About clock skew of interface SystemVerilog SystemVerilog , interface , skews	0	192	September 14, 2023
How can I loop through a series of separate interfaces? SystemVerilog SystemVerilog , interface , generate-block , for-loop , iteration	0	372	May 16, 2023
Access internal signals wire/reg of DUT in interface SystemVerilog SystemVerilog , interface	1	374	May 9, 2023
Use interface signals as inout in systemverilog SystemVerilog SystemVerilog , interface , bus-functional-model , coverage-UVM-module-class	3	555	April 3, 2023
D Flip Flop Design without SV TB Environment SystemVerilog SystemVerilog , System-Verilog , modport , interface	3	687	December 26, 2022
How use interface in verification of a module that has not use interface? SystemVerilog SystemVerilog , interface	1	324	December 20, 2022
Dynamic array concatenation problem SystemVerilog SystemVerilog , interface , dynamic	3	607	December 10, 2022
Memory verification SystemVerilog SystemVerilog , interface	4	637	October 9, 2022
Spy Interface SystemVerilog SystemVerilog , interface , FIFO-UVM-VIRTUAL-INTERFACE	2	581	August 17, 2022
Port directions in an interface with modports UVM SystemVerilog , UVM , interface	5	669	July 13, 2022
Assign to interface input inside Class SystemVerilog SystemVerilog , class , interface , systemverilog-interface , assignment	3	410	June 14, 2022
Difference between input and wire clock to an interface SystemVerilog SystemVerilog , interface	4	977	May 19, 2022
Interface design for an unidirectional bus SystemVerilog SystemVerilog , interface , BFM , pullup , bidirectional-bus	1	681	August 31, 2021
Compiling a package and an interface into a library SystemVerilog SystemVerilog , Package , interface , compilation , library	1	720	August 13, 2021
Best Interface Sharing Technique between IP/Sub-System and SOC Flows? UVM UVM , interface , uvm-harness	6	2048	August 13, 2021
Question on the use of interfaces to bundle up vectors SystemVerilog SystemVerilog , hierarchy , interface	1	487	July 14, 2021
How to connect unconstrained array of VHDL records to SV interface SystemVerilog SystemVerilog , interface , vhdl-record-element-connect-systemverilog	1	708	June 20, 2021
Port mismatch while connect interface and dut SystemVerilog SystemVerilog , wire , logic , interface	3	2587	June 6, 2021
How to connect bi-directional signal UVM UVM , interface , systemverilog-uvm , bidirectional-port-inout-driver-interface	4	1640	May 24, 2021
Interface Port connection through a generate or array instance SystemVerilog SystemVerilog , interface , systemverilog-generate	0	863	April 17, 2021
How to connect the inout port of class interface to inout port of module SystemVerilog SystemVerilog , interface , Inout-port	3	5748	April 5, 2021
Hierarchical access to a coverpoint from interface UVM SystemVerilog , UVM , Coverage , hierarchy , interface	1	694	January 16, 2021