Illegal combination of procedural drivers
|
|
3
|
138
|
October 28, 2024
|
Interface Array and Generic Interface
|
|
2
|
84
|
October 16, 2024
|
Check the interface type using parameterized interface
|
|
2
|
133
|
July 8, 2024
|
Parameter type in interface
|
|
1
|
205
|
April 16, 2024
|
"Undefined module: <interface> was used. Port connection rules will not be checked at such instantiations."
|
|
2
|
273
|
March 27, 2024
|
Task arguments behaviour in SV interface
|
|
5
|
320
|
February 28, 2024
|
Assign parameter in interface
|
|
5
|
324
|
February 18, 2024
|
Error during testbench to dut connection using asbtract class + interfaces
|
|
4
|
309
|
December 29, 2023
|
Interface modport: one signal always connected to a default value
|
|
5
|
553
|
November 29, 2023
|
Interface direct connection at top level
|
|
1
|
296
|
October 5, 2023
|
Interface BFM and port direction
|
|
1
|
384
|
September 23, 2023
|
About clock skew of interface
|
|
0
|
303
|
September 14, 2023
|
How can I loop through a series of separate interfaces?
|
|
0
|
587
|
May 16, 2023
|
Access internal signals wire/reg of DUT in interface
|
|
1
|
505
|
May 9, 2023
|
Use interface signals as inout in systemverilog
|
|
3
|
812
|
April 3, 2023
|
D Flip Flop Design without SV TB Environment
|
|
3
|
1034
|
December 26, 2022
|
How use interface in verification of a module that has not use interface?
|
|
1
|
398
|
December 20, 2022
|
Dynamic array concatenation problem
|
|
3
|
909
|
December 10, 2022
|
Memory verification
|
|
4
|
866
|
October 9, 2022
|
Spy Interface
|
|
2
|
755
|
August 17, 2022
|
Port directions in an interface with modports
|
|
5
|
960
|
July 13, 2022
|
Assign to interface input inside Class
|
|
3
|
588
|
June 14, 2022
|
Difference between input and wire clock to an interface
|
|
4
|
1384
|
May 19, 2022
|
Interface design for an unidirectional bus
|
|
1
|
832
|
August 31, 2021
|
Compiling a package and an interface into a library
|
|
1
|
1030
|
August 13, 2021
|
Best Interface Sharing Technique between IP/Sub-System and SOC Flows?
|
|
6
|
2394
|
August 13, 2021
|
Question on the use of interfaces to bundle up vectors
|
|
1
|
620
|
July 14, 2021
|
How to connect unconstrained array of VHDL records to SV interface
|
|
1
|
874
|
June 20, 2021
|
Port mismatch while connect interface and dut
|
|
3
|
3041
|
June 6, 2021
|
How to connect bi-directional signal
|
|
4
|
1969
|
May 24, 2021
|