Topics tagged interface

Topic	Replies	Views	Activity
Illegal combination of procedural drivers SystemVerilog interface , struct	3	397	October 28, 2024
Interface Array and Generic Interface SystemVerilog SystemVerilog , interface , Bus-interface	2	157	October 16, 2024
Check the interface type using parameterized interface SystemVerilog SystemVerilog , interface	2	155	July 8, 2024
Parameter type in interface SystemVerilog SystemVerilog , interface	1	234	April 16, 2024
"Undefined module: <interface> was used. Port connection rules will not be checked at such instantiations." UVM SystemVerilog , UVM , configuration , virtual-interface , interface	2	320	March 27, 2024
Task arguments behaviour in SV interface SystemVerilog SystemVerilog , interface	5	471	February 28, 2024
Assign parameter in interface SystemVerilog parameter , interface	5	408	February 18, 2024
Error during testbench to dut connection using asbtract class + interfaces SystemVerilog interface , Abstract-class , pure-virtual-methods	4	369	December 29, 2023
Interface modport: one signal always connected to a default value SystemVerilog SystemVerilog , interface , SystemVerilog-modport	5	602	November 29, 2023
Interface direct connection at top level SystemVerilog SystemVerilog , interface	1	320	October 5, 2023
Interface BFM and port direction SystemVerilog SystemVerilog , interface , clockingblock	1	405	September 23, 2023
About clock skew of interface SystemVerilog SystemVerilog , interface , skews	0	309	September 14, 2023
How can I loop through a series of separate interfaces? SystemVerilog SystemVerilog , interface , generate-block , for-loop , iteration	0	622	May 16, 2023
Access internal signals wire/reg of DUT in interface SystemVerilog SystemVerilog , interface	1	527	May 9, 2023
Use interface signals as inout in systemverilog SystemVerilog SystemVerilog , interface , bus-functional-model , coverage-UVM-module-class	3	911	April 3, 2023
D Flip Flop Design without SV TB Environment SystemVerilog SystemVerilog , System-Verilog , modport , interface	3	1092	December 26, 2022
How use interface in verification of a module that has not use interface? SystemVerilog SystemVerilog , interface	1	402	December 20, 2022
Dynamic array concatenation problem SystemVerilog SystemVerilog , interface , dynamic	3	965	December 10, 2022
Memory verification SystemVerilog SystemVerilog , interface	4	897	October 9, 2022
Spy Interface SystemVerilog SystemVerilog , interface , FIFO-UVM-VIRTUAL-INTERFACE	2	772	August 17, 2022
Port directions in an interface with modports UVM SystemVerilog , UVM , interface	5	1010	July 13, 2022
Assign to interface input inside Class SystemVerilog SystemVerilog , class , interface , systemverilog-interface , assignment	3	601	June 14, 2022
Difference between input and wire clock to an interface SystemVerilog SystemVerilog , interface	4	1511	May 19, 2022
Interface design for an unidirectional bus SystemVerilog SystemVerilog , interface , BFM , pullup , bidirectional-bus	1	847	August 31, 2021
Compiling a package and an interface into a library SystemVerilog SystemVerilog , Package , interface , compilation , library	1	1146	August 13, 2021
Best Interface Sharing Technique between IP/Sub-System and SOC Flows? UVM UVM , interface , uvm-harness	6	2495	August 13, 2021
Question on the use of interfaces to bundle up vectors SystemVerilog SystemVerilog , hierarchy , interface	1	637	July 14, 2021
How to connect unconstrained array of VHDL records to SV interface SystemVerilog SystemVerilog , interface , vhdl-record-element-connect-systemverilog	1	898	June 20, 2021
Port mismatch while connect interface and dut SystemVerilog SystemVerilog , wire , logic , interface	3	3174	June 6, 2021
How to connect bi-directional signal UVM UVM , interface , systemverilog-uvm , bidirectional-port-inout-driver-interface	4	2049	May 24, 2021

Illegal combination of procedural drivers

SystemVerilog

interface , struct

3

397

October 28, 2024

Interface Array and Generic Interface

SystemVerilog

SystemVerilog , interface , Bus-interface

2

157

October 16, 2024

Check the interface type using parameterized interface

SystemVerilog

SystemVerilog , interface

2

155

July 8, 2024

Parameter type in interface

SystemVerilog

SystemVerilog , interface

1

234

April 16, 2024

"Undefined module: <interface> was used. Port connection rules will not be checked at such instantiations."

UVM

SystemVerilog , UVM , configuration , virtual-interface , interface

2

320

March 27, 2024

Task arguments behaviour in SV interface

SystemVerilog

SystemVerilog , interface

5

471

February 28, 2024

Assign parameter in interface

SystemVerilog

parameter , interface

5

408

February 18, 2024

Error during testbench to dut connection using asbtract class + interfaces

SystemVerilog

interface , Abstract-class , pure-virtual-methods

4

369

December 29, 2023

Interface modport: one signal always connected to a default value

SystemVerilog

SystemVerilog , interface , SystemVerilog-modport

5

602

November 29, 2023

Interface direct connection at top level

SystemVerilog

SystemVerilog , interface

1

320

October 5, 2023

Interface BFM and port direction

SystemVerilog

SystemVerilog , interface , clockingblock

1

405

September 23, 2023

About clock skew of interface

SystemVerilog

SystemVerilog , interface , skews

0

309

September 14, 2023

How can I loop through a series of separate interfaces?

SystemVerilog

SystemVerilog , interface , generate-block , for-loop , iteration

0

622

May 16, 2023

Access internal signals wire/reg of DUT in interface

SystemVerilog

SystemVerilog , interface

1

527

May 9, 2023

Use interface signals as inout in systemverilog

SystemVerilog

SystemVerilog , interface , bus-functional-model , coverage-UVM-module-class

3

911

April 3, 2023

D Flip Flop Design without SV TB Environment

SystemVerilog

SystemVerilog , System-Verilog , modport , interface

3

1092

December 26, 2022

How use interface in verification of a module that has not use interface?

SystemVerilog

SystemVerilog , interface

1

402

December 20, 2022

Dynamic array concatenation problem

SystemVerilog

SystemVerilog , interface , dynamic

3

965

December 10, 2022

Memory verification

SystemVerilog

SystemVerilog , interface

4

897

October 9, 2022

Spy Interface

SystemVerilog

SystemVerilog , interface , FIFO-UVM-VIRTUAL-INTERFACE

2

772

August 17, 2022

Port directions in an interface with modports

UVM

SystemVerilog , UVM , interface

5

1010

July 13, 2022

Assign to interface input inside Class

SystemVerilog

SystemVerilog , class , interface , systemverilog-interface , assignment

3

601

June 14, 2022

Difference between input and wire clock to an interface

SystemVerilog

SystemVerilog , interface

4

1511

May 19, 2022

Interface design for an unidirectional bus

SystemVerilog

SystemVerilog , interface , BFM , pullup , bidirectional-bus

1

847

August 31, 2021

Compiling a package and an interface into a library

SystemVerilog

SystemVerilog , Package , interface , compilation , library

1

1146

August 13, 2021

Best Interface Sharing Technique between IP/Sub-System and SOC Flows?

UVM

UVM , interface , uvm-harness

6

2495

August 13, 2021

Question on the use of interfaces to bundle up vectors

SystemVerilog

SystemVerilog , hierarchy , interface

1

637

July 14, 2021

How to connect unconstrained array of VHDL records to SV interface

SystemVerilog

SystemVerilog , interface , vhdl-record-element-connect-systemverilog

1

898

June 20, 2021

Port mismatch while connect interface and dut

SystemVerilog

SystemVerilog , wire , logic , interface

3

3174

June 6, 2021

How to connect bi-directional signal

UVM

UVM , interface , systemverilog-uvm , bidirectional-port-inout-driver-interface

4

2049

May 24, 2021