Illegal combination of procedural drivers

SystemVerilog
,
1

I’m getting a warning from the compiler about an illegal combination of procedural drivers for an interface signal. One of the drivers is the DUT, and the other driver is the clocking block defined inside the interface itself.

This interface defines the signaling for bidirectional communication between a source and a sink. For this warning, my DUT is the sink - but the compiler is complaining about the source clocking block. Even though the source clocking block is defined in the interface, I know it will never be used in this testbench. So do I just ignore the warnings? Or is there a better approach here that I’m not considering? I don’t want to add `ifdefs to the interface itself because 1. that’s gross, and 2. that’s not scalable to all of our interfaces.

I can’t just change the interface signals from variables (logic) to nets (wire) because the interface instantiates structs, which must encapsulate variables.

2

You should use wires for your connections along with a state variable that determines if the interface is driving the wire or the DUT.

typedef enum {MASTER, SLAVE} mode_t;

interface my_interface;
  wire inout0;
  wire inout1;

  mode_t mode = MASTER;

  reg inout0_r;
  reg inout1_r;

  assign inout0 = (mode == MASTER) ? inout0_r : 'z;
  assign inout1 = (mode == MASTER) ? inout1_r : 'z;
endinterface

Your code can read the wires as inputs, and drive the regs when acting as a MASTER.

3

Thanks @cgales. What’s stopping me from using wires for the connection is that the interface contains structs.

struct packed {
  wire sig1;
  wire sig2;
} txn_s

That code will always produce a syntax error because we can only put variables in a struct. Is there some other way to encapsulate wires?

4

I’m not sure what your exact requirements are, but you can assign the wires from a struct:

typedef enum {MASTER, SLAVE} mode_t;

typedef struct packed {
  reg sig1;
  reg sig2;
} txn_t;

interface my_interface;
  wire inout0;
  wire inout1;

  wire sig1;
  wire sig2;
  
  mode_t mode = MASTER;

  reg inout0_r;
  reg inout1_r;
  
  txn_t txn;

  assign inout0 = (mode == MASTER) ? inout0_r : 'z;
  assign inout1 = (mode == MASTER) ? inout1_r : 'z;
  
  assign sig1 = (mode == MASTER) ? txn.sig1 : 'z;
  assign sig2 = (mode == MASTER) ? txn.sig2 : 'z;
endinterface