Topic	Replies	Views	Activity
Signal written by more than one continuous statement SystemVerilog SystemVerilog , questasim , Polymorphism , BFM , sv-interfaces	4	2878	October 24, 2024
Difference between BFM and VIP UVM UVM , BFM	1	710	February 22, 2023
What exactly BFM contain? UVM UVM , BFM	1	600	October 2, 2021
Can BFM agent have multiple driver/sequencer for multiple interfaces? UVM UVM , BFM	1	697	September 21, 2021
Interface design for an unidirectional bus SystemVerilog SystemVerilog , interface , BFM , pullup , bidirectional-bus	1	821	August 31, 2021
Bus Functional model UVM UVM , BFM	1	688	March 7, 2021
Difference between API and Virtual Interface UVM UVM , BFM	2	925	January 31, 2020
Using BFM Verification IP in system verilog code SystemVerilog SystemVerilog , BFM	1	1388	November 18, 2019
Communication between generator and BFM SystemVerilog SystemVerilog , mailbox , static , BFM , communication-sv	1	978	June 3, 2019
UVM UVM UVM , BFM	1	1314	June 6, 2018
Bus function modeling UVM UVM , BFM	2	1529	January 5, 2018
Best way of asserting a sequence SystemVerilog SystemVerilog , assertion , BFM	3	2987	November 25, 2017
UVM possible to use same Driver/Monitor for different interfaces using abstract classes? UVM UVM , uvm-agent , BFM , config	2	3202	April 8, 2017
What is a Bus Functional Model (BFM)? SystemVerilog SystemVerilog , BFM , bus-functional-model , testbench-architecture	3	32488	January 1, 2017
What is the difference between driver and BFM? UVM UVM , driver , BFM	2	11723	March 21, 2016

BFM