Using BFM Verification IP in system verilog code

SystemVerilog
,
1

Hi all,
I am new to system verilog.
I was writing a test bench to test my SPI master code . I came across something called as BFM provided by SysWip(http://syswip.com/)
It gives, master and slave Verification IP folders. The folders have an interface and a package file.

I have a question here, to test my master code, i will have to make use of only the slave verification IP…am i right?

also how is the connection made to the interface? How do i instantiate the interfce and in which file the connections are done.
Below is a part of my master.sv amd master_tb.sv code.

module master
	(
		input clk,
		output sdi,
		input sdo,
		output sclk,
		output [SLAVES-1:0] slave_select
	); 

//internal signals
//code to shift in and out data
...

module master_tb();
reg clk;
reg sdo;
wire sdi;
wire sclk;
wire [2:0] slave_select;

//part of my testbench code i have typed here.
master_tb dut(
            .clk(clk),
            .sclk(sclk),
            ....
             );

My question is,

  1. where do i import the interface, in which file?
  2. do i need both the interfaces-master and slave?
  3. how do i do the connections?
  4. How do i do the data transfer?
2

In reply to Newbie1192:

Start Here.