The Introduction to the UVM (Universal Verification Methodology) course consists of twelve sessions that will guide you from rudimentary SystemVerilog through a complete UVM testbench. Each session is designed to give you the minimal amount of knowledge necessary to make it to the next level. Once you have worked through all these sessions, you will have experience with all the major components of the UVM as well as their concepts. You are then ready to learn more advanced techniques.
You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses. Upon completion of the Introduction to the UVM Course, you are encouraged to view Basic UVM and Advanced UVM.
