FPGA Verification

The definition of what FPGA really means has changed dramatically over the last two decades. Whether blazing the trail or being on the trailing edge of Moore’s Law, this is an exciting time to be an FPGA Designer. New opportunities bring new challenges for the FPGA market. As devices grow and become more complex resembling complete systems, the task of verifying such a system becomes daunting. In this section you will find timely, unbiased information from subject-matter experts that will help you navigate through this ever-changing landscape.

The modern FPGA designer faces many different challenges while working on his or her project. Fortunately, there are many solutions to choose from and more powerful, user-friendly tools available. Come back to this section often for new information and stay ahead of your competition.

FPGA Verification Courses

Introduction to the UVM

The Introduction to the UVM course consists of twelve sessions that will guide you from rudimentary SystemVerilog through a complete UVM testbench.

Assertion-Based Verification

This course introduces a set of steps for advancing an organization’s assertion-based-verification (ABV) skills, infrastructure, and metrics.

VHDL-2008 Why It Matters

VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages.

Evolving FPGA Verification Capabilities

This course introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.

Questa® FPGA Resources

ModelSim's easy to use, unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment

Modelsim® HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused.

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