FPGA Verification With Assertions: Why Bother?
The benefits assertion-based verification (ABV) have been talked about for years. However, for many FPGA engineers with little time available to learn newer advanced functional verification techniques, assertions seem overly complex—and the method of creating them remains a mystery. This paper provides a practical, easy, step-by-step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions.
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Improving FPGA Debugging with Assertions.
Here's one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics. In fact, Gartner reported that FPGAs now have a 30-to-1 edge over ASICs in terms of new design starts. This ratio is startling since FPGAs have traditionally been relegated to glue logic, low-volume production, or prototype parts used for analysis. But the landscape is changing.
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