Testbench Architecture
This chapter covers the basics and details of UVM testbench architecture, construction, and leads into other chapters covering each of the constituent parts of a typical UVM testbench.
A UVM testbench is built using SystemVerilog (dynamic) class objects interacting with SystemVerilog (static) interfaces and modules in a structured hierarchy. The hierarchy is composed of layers of functionality. At the center of the testbench is the Design Under Test (DUT).
