Academy Topics | Verification Academy

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Acceleration

Acceleration are techniques that are used to address performance shortcomings of traditional simulation.

Coverage

Coverage is a simulation metric we use to measure verification progress and completeness.

Debug takes a significant proportion of any design or verification engineer’s time. An Intuitive and powerful HW and SW debug solution is needed to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms.

Design and Verification Languages

Verification languages are the foundation of the very dynamic electronics industry.

Formal-Based Techniques

This topic area focuses on formal-based techniques, ranging from formal property checking to formal coverage closure to sequential logic equivalence checking.

FPGA Verification

The modern FPGA designer faces many different challenges while working on his or her project. Fortunately, there are many solutions to choose from and more powerful, user-friendly tools available.

Functional Safety

The core mission of every safety-critical standard is to ensure the absence of unreasonable risk due to malfunctioning systems resulting in damage to persons or property.

Planning, Measurement and Analysis

This topic area focuses on the early stages of a verification project.

Portable Test and Stimulus

Portable Stimulus Standard (PSS) can automate the process to maximize coverage and ensure the most efficient execution of a wide range of tests on multiple platforms.

Simulation-Based Techniques

This topic area focuses on simulation-based techniques, ranging from stimulus generation, coverage modeling, and correctness checking

Static-Based Techniques

This topic focuses on static verification techniques such as Clock-Domain Crossing (CDC), Reset Domain Crossing (RDC), linting, as well as power-aware and gate-level domain crossing analyses.

UVM Connect

UVM Connect is an open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components.

UVM Framework

The UVM Framework is an open-source package that provides a reusable UVM methodology and code generator that provides rapid testbench generation.

UVM - Universal Verification Methodology

Here you’ll find everything you need to get up to speed on UVM, whether it’s downloading the kit(s), viewing a cookbook article, downloading a UVM video course and more.

Verification IP

Siemens EDA’s Questa Verification IP (QVIP) integrates seamlessly into all advanced verification environments on any simulator.

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