Topics tagged systemverilog

Topic	Replies	Views	Activity
Interview question on constraint SystemVerilog SystemVerilog , constraints , uvm-sv-constraints	24	12000	January 20, 2026
Assertion question :- SystemVerilog SystemVerilog , assertion , System-Verilog , systemverilogassertionSVA	9	493	January 18, 2026
SystemVerilog constraint: unique addr across array of structs without auxiliary array SystemVerilog SystemVerilog , constraint-randomization , unique	3	78	January 9, 2026
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	2	583	January 7, 2026
Assertion error SystemVerilog SystemVerilog , UVM , assertion , SVA	3	33	January 5, 2026
Sequence which admits : No match v/s Hard Zero SystemVerilog SystemVerilog , assertion , SVA	8	400	December 27, 2023
Semaphore put method question SystemVerilog SystemVerilog , System-Verilog , semaphore-keys , semaphore-with-multiple-keys	5	419	December 28, 2025
SVA to check a N-stage synchronizer output SystemVerilog SystemVerilog , assertion , System-Verilog , SVA , SVA-Assertion	9	74	December 18, 2025
Connection using modports with different signals SystemVerilog SystemVerilog , modport , interface	6	55	December 12, 2025
Deep copy using shallow copy SystemVerilog SystemVerilog	1	59	December 6, 2025
Once a certain sequence occurs that another seq shouldn't occur till simulation ends SystemVerilog SystemVerilog , Once-a-certain-sequence-occurs-that-another-seq-shouldnt-occur-till-simulation-ends	8	662	December 4, 2025
Adding and deleting elements of dynamic type at same time SystemVerilog SystemVerilog , Queues , Dynamic-Array	2	69	November 29, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	63	November 17, 2025
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses UVM SystemVerilog , UVM , uvm-register-model	2	68	November 13, 2025
Individual field access causes extra reads/writes? UVM SystemVerilog , UVM , uvm-register-model	5	45	November 12, 2025
Resume simulation when any 2 threads out of 3 get completed within fork-join_any SystemVerilog SystemVerilog , fork-join_any	9	4220	November 12, 2025
Question regarding followed by operator in SVA (#-# and #=# SystemVerilog SystemVerilog , SVA , SVA-Assertion	0	56	November 11, 2025
System verilog constraint help SystemVerilog SystemVerilog , constraint-randomization	2	111	November 11, 2025
Chained Implications in SVA SystemVerilog SystemVerilog , Coverage , assertion , SVA , axi , AHB	0	57	November 3, 2025
Why only ##1 (single delay operator) used in the case of multiple clock sequences? SystemVerilog SystemVerilog , assertion	2	674	November 3, 2025
restricting sequence as long as one variable is asserted SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	4	72	November 2, 2025
Paper: Understanding SVA Degeneracy SystemVerilog SystemVerilog , SystemVerilog-SVA	9	598	October 29, 2025
Multiple analysis ports to single implementation UVM SystemVerilog , UVM , analysis-port	8	198	October 23, 2025
How to properly extend a test case from different parents UVM SystemVerilog , UVM	2	129	October 21, 2025
How to deep copy UVM transaction containing queue of objects? UVM SystemVerilog , UVM	3	83	October 21, 2025
Is there an alternative to sum() Constraint SystemVerilog SystemVerilog , Is-there-an-alternative-to-sum-Constraint	5	1883	October 19, 2025
What operators constitute a multi-threaded sequence SystemVerilog SystemVerilog , SVA , multi-threaded-antecedent , multi-threaded-assertion	1	66	October 16, 2025
Config db fatal isssue UVM OVM , SystemVerilog , UVM	1	73	October 16, 2025
Getting last transaction in consumer repetitively even though producer is sending all transaction UVM SystemVerilog , UVM	3	79	October 15, 2025
SystemVerilog reason of not putting always in program block SystemVerilog SystemVerilog	1	79	October 15, 2025