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SVA to check a N-stage synchronizer output
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9
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46
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December 18, 2025
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Connection using modports with different signals
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6
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38
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December 12, 2025
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Deep copy using shallow copy
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1
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38
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December 6, 2025
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Once a certain sequence occurs that another seq shouldn't occur till simulation ends
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8
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643
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December 4, 2025
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Adding and deleting elements of dynamic type at same time
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2
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51
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November 29, 2025
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What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules?
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0
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47
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November 17, 2025
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UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses
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2
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55
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November 13, 2025
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Individual field access causes extra reads/writes?
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5
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39
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November 12, 2025
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Resume simulation when any 2 threads out of 3 get completed within fork-join_any
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9
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4192
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November 12, 2025
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Question regarding followed by operator in SVA (#-# and #=#
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0
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49
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November 11, 2025
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System verilog constraint help
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2
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93
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November 11, 2025
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Chained Implications in SVA
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0
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49
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November 3, 2025
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Why only ##1 (single delay operator) used in the case of multiple clock sequences?
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2
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667
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November 3, 2025
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restricting sequence as long as one variable is asserted
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4
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69
|
November 2, 2025
|
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Paper: Understanding SVA Degeneracy
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9
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587
|
October 29, 2025
|
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Multiple analysis ports to single implementation
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8
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171
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October 23, 2025
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How to properly extend a test case from different parents
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2
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119
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October 21, 2025
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How to deep copy UVM transaction containing queue of objects?
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3
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73
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October 21, 2025
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Is there an alternative to sum() Constraint
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5
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1872
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October 19, 2025
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What operators constitute a multi-threaded sequence
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1
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62
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October 16, 2025
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Config db fatal isssue
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1
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60
|
October 16, 2025
|
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Getting last transaction in consumer repetitively even though producer is sending all transaction
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3
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71
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October 15, 2025
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SystemVerilog reason of not putting always in program block
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1
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69
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October 15, 2025
|
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Excluding the already defined bins
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5
|
57
|
October 12, 2025
|
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Need clarification on static method and non static method
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11
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4304
|
October 12, 2025
|
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Random stability with non-random object
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2
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36
|
October 8, 2025
|
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Assertion for clock gating
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1
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72
|
October 3, 2025
|
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Dynamic Array- System Verilog
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1
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85
|
September 30, 2025
|
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What are different types of temporal Operators in SystemVerilog
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3
|
98
|
September 29, 2025
|
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Constraints on array elements
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6
|
4585
|
September 28, 2025
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