Making a generic adapter for different interfaces specific

SystemVerilog
,
1

Hello!

I have an adapter module that connects signals of different definitions of the AXI interface. I am using a generic declaration of the ports (interface keyword) to be able to pass any kind of interface.

I want to replace the generic ports with a specific interface definition passed as a parameter. Is this possible?

Why?
For some synthesis constraints, I need the ports inside the generic adapter to be specific

What I have:

module axi_intf_adapter #(
    ...
  )(
    interface  master,
    interface  slave
  );

// connection signals
...

What I want to achieve:

module axi_intf_adapter #(
    parameter xx master_if,
    parameter xx slave_if,
    ...
  )(
    master_if  master,
    slave_if     slave
  );

// connection signals
...
2

An interface is not a data type, thus cannot be a type parameter.

If the module is not a top-level module, the generic interface assumes the specific interface it is connected to. For top-level modules, some synthesis tools provide a mechanism for specifying the specific interface.

3

thanks for your prompt answer Dave!

So you are saying theoretically there is no way to implement that in the code, correct?

4

That is correct. Although I would say that you shouldn’t have a need to implement that in code.