Topics tagged Interfaces

Topic	Replies	Views	Activity
Parametrized interfaces SystemVerilog Interfaces	1	424	January 10, 2024
SV Interfaces: best coding style to encapsulate functionality? SystemVerilog SystemVerilog , Interfaces	8	1498	October 12, 2023
How can I assign one interface to another interface without manually connecting all signals? SystemVerilog SystemVerilog , Interfaces	11	14951	August 30, 2022
System Verilog Interface used in multiple places SystemVerilog SystemVerilog , Interfaces , dave_rich	1	608	May 12, 2021
Why extern forkjoin function won't work in interface? SystemVerilog SystemVerilog , functions-in-system-verilog , Interfaces	1	782	February 23, 2021
SystemVerilog Interface Syntesis SystemVerilog SystemVerilog , HDL-designer-systemverilog-interface , Interfaces , synthesis	7	1547	November 22, 2019
Interface function with type parameter SystemVerilog SystemVerilog , Interfaces	1	957	July 19, 2019
Driving a wire from a task in an interface SystemVerilog SystemVerilog , wire , Compilation-Error , Interfaces	11	8289	July 1, 2019
Multi dimensional array of interfaces SystemVerilog SystemVerilog , Interfaces	7	3681	July 24, 2017
Driving a single signal with multiple interfaces UVM UVM , Interfaces , multiply-driven-signals , Sharing-signals	7	4727	February 13, 2017
Is there any way to store a reference to a variable? SystemVerilog SystemVerilog , Interfaces , Passing-by-reference	1	7129	February 9, 2017