wire
Topic | Replies | Views | Activity | |
---|---|---|---|---|
Reg vs wire vs logic @SystemVerilog | 1 | 21861 | December 28, 2013 | |
How wire stores Z | 3 | 487 | December 29, 2022 | |
Wire declaration inside SV class | 2 | 892 | March 3, 2022 | |
Port mismatch while connect interface and dut | 3 | 2587 | June 6, 2021 | |
Driving a wire from a task in an interface | 11 | 7797 | July 1, 2019 | |
Wire vs Logic | 2 | 16954 | February 11, 2018 | |
Why can't I pass the type wire as a parameter to an interface? | 1 | 1822 | February 14, 2017 |