Topics tagged wire

Topic	Replies	Views	Activity
Reg vs wire vs logic @SystemVerilog SystemVerilog SystemVerilog , reg , wire , logic	1	22219	December 28, 2013
How wire stores Z SystemVerilog SystemVerilog , wire , default-value	3	752	December 29, 2022
Wire declaration inside SV class SystemVerilog SystemVerilog , wire , base-class	2	1218	March 3, 2022
Port mismatch while connect interface and dut SystemVerilog SystemVerilog , wire , logic , interface	3	3122	June 6, 2021
Driving a wire from a task in an interface SystemVerilog SystemVerilog , wire , Compilation-Error , Interfaces	11	8566	July 1, 2019
Wire vs Logic SystemVerilog SystemVerilog , wire , logic , Mapping-data-types , ports	2	17263	February 11, 2018
Why can't I pass the type wire as a parameter to an interface? SystemVerilog SystemVerilog , wire , parameterized-interface , syntax-error	1	2034	February 14, 2017