Reg vs wire vs logic @SystemVerilog

SystemVerilog
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Hi All,

As for the difference between usage of the ‘reg’ and ‘wire’ @Verilog, I aware of…

But what’s the difference between the wire and logic @SystemVerilog? Why an additional data type ‘logic’ was required?

What’s the data type in SystemVerilog, wch is similar to ‘reg’ in Verilog?

Thank you!

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The only difference between reg and logic in SystemVerilog is how they are spelled. See What's the deal with those wire’s and reg’s in Verilog - Verification Horizons