How wire stores Z

SystemVerilog
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1

If wire data type cannot store value how it is storing Z value?

2

In reply to shiva kumar:

A wire is not a data type, it is a kind of signal whose value is the result of a built-in resolution of all the drivers on the wire. The result of that resolution function has a 4-state logic data type (0, 1, X, Z) where the Z state represent the case when there or no active drivers (a driver assigning a Z state is considered an inactive driver).

You may want to read:

3

I think you are confusing the word “stores” with “holds”. A wire holds a value which is driven on it. For example if you say assign wireA= regA + regB, the wireA always hold a value which is the sum of values “stored” in regA and regB.

If a wire is not driven at any point in the simulation, it holds a default value of “z”. (Remember this is a 4-state wire and therefore it has to hold one of the 4 values).

Hope this helps

Logie Ramachandran
Accelver Systems Inc

4

In reply to logie:

So by default wire has capability to hold Z value
Thank You