Topics tagged base-class

Topic	Replies	Views	Activity
Virtual function in system verilog UVM UVM , System-Verilog , base-class , virtual-function	7	1398	March 22, 2022
Wire declaration inside SV class SystemVerilog SystemVerilog , wire , base-class	2	1259	March 3, 2022
Inheritance and nesting notation of classes in UVM UVM UVM , base-class , instance-name , assigning-class-instances , notation-uvm	3	4200	June 23, 2016
Passing derived class transactions to a base class analysis port UVM UVM , casting , tlm_fifo , base-class , derived-class	2	2252	May 17, 2014