base-class
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| Virtual function in system verilog |
|
7 | 1391 | March 22, 2022 |
| Wire declaration inside SV class |
|
2 | 1250 | March 3, 2022 |
| Inheritance and nesting notation of classes in UVM |
|
3 | 4174 | June 23, 2016 |
| Passing derived class transactions to a base class analysis port |
|
2 | 2250 | May 17, 2014 |