Wire declaration inside systemverilog class is illegal. Please help explaining why is it illegal.
Thank you.
In reply to mannat:
wire is static, class is dynamic.
instantiate a class that contains wire makes no sense.
In reply to mannat:
Wire declaration inside systemverilog class is illegal. Please help explaining why is it illegal.
Because This Is The Way.
Sorry for that abrupt response, but there is no good reason other than that’s the way the language has been set up since its inception. A wire represents a network of connections as well as a value. A wire does not store any values; it value is the resolution of all the drivers in the network. The network gets created at elaboration before simulation begins. The language has no provisions for modifying a network at runtime, except for maybe a force statement.
SystemVerilog has reduced the need for wires except for special cases where you need multiple drivers on the network. I guess that might be a good reason why there is no need to add wires to classes.