Wire vs Logic

SystemVerilog
, , , ,
1

Hello guys

Can anyone explain whats the basic difference between wire and logic?
How type and data type is differentiated?
I know var / wire is a type and logic / bit / byte / … are all data types, but whats the difference between both??

And please let me know why am getting error on the below code!!!

module strobe_test(input logic a, b, clk, output logic y);
always_ff @(posedge clk) begin
	y <= a + b;
end

initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
	a = 0; b = 0;
	#10 a = 0; b = 1;
	#10 a = 1; b = 0;
	#10 a = 1; b = 1;
	#20 $stop;
end


endmodule : strobe_test

Errors →

– Compiling module strobe_test

** Error: strobe_test.sv(7): (vlog-2110) Illegal reference to net “clk”.

** Error: strobe_test.sv(8): (vlog-2110) Illegal reference to net “clk”.

** Error: strobe_test.sv(12): (vlog-2110) Illegal reference to net “a”.

** Error: strobe_test.sv(12): (vlog-2110) Illegal reference to net “b”.

** Error: strobe_test.sv(13): (vlog-2110) Illegal reference to net “a”.

** Error: strobe_test.sv(13): (vlog-2110) Illegal reference to net “b”.

** Error: strobe_test.sv(14): (vlog-2110) Illegal reference to net “a”.

** Error: strobe_test.sv(14): (vlog-2110) Illegal reference to net “b”.

** Error: strobe_test.sv(15): (vlog-2110) Illegal reference to net “a”.

** Error: strobe_test.sv(15): (vlog-2110) Illegal reference to net “b”.

And someone please explain what would be the default type and data type of ports, how port definitions vary on the usage of the same??

Thanks
Manjush

2

In reply to manjush_pv:

See What's the deal with those wire’s and reg’s in Verilog - Verification Horizons and Usage of Var - SystemVerilog - Verification Academy

3

In reply to dave_59:

Thanks Dave, that helped a much.