Verification Academy

ports

Topic		Replies	Views	Activity
Wire vs Logic SystemVerilog SystemVerilog , wire , logic , Mapping-data-types , ports		2	17264	February 11, 2018
UVM ports max_size argument UVM UVM , ports , max_size , connection		5	1993	December 12, 2016
Driver with two sequencer UVM UVM , sequencer , driver , item , ports		2	3515	March 25, 2016