ports

Topic Replies Views Activity
SystemVerilog
SystemVerilog ,  wire ,  logic ,  Mapping-data-types ,  ports
2 17285 February 11, 2018
UVM
UVM ,  ports ,  max_size ,  connection
5 2001 December 12, 2016
UVM
UVM ,  sequencer ,  driver ,  item ,  ports
2 3518 March 25, 2016