Topics tagged syntax-error

Topic	Replies	Views	Activity
Error-[SE] Syntax error UVM UVM , syntax-error	13	10016	November 12, 2021
Syntax error in a code block UVM SystemVerilog , UVM , syntax-error	3	1467	August 20, 2020
Want to know to purpose of the `" syntax SystemVerilog SystemVerilog , syntax-error	1	614	February 20, 2020
Why can't I pass the type wire as a parameter to an interface? SystemVerilog SystemVerilog , wire , parameterized-interface , syntax-error	1	2017	February 14, 2017