Want to know to purpose of the `" syntax

SystemVerilog
,
1

In my project i am not able interpret the logic due to the some syntax, ex
Syntax is
" <signal hierarchy> "
My question is what is the use of `" in start and end of the line.
Thanks

2

In reply to Bhaskar_nxp:

It would help if you showed where you saw this syntax. You should only see this "** syntax inside the definition of a **define macro. Normally the macro processor passes a quoted “string” with no interpretation of the text inside the string. The `" says to process the string text looking for other macros and arguments. For example

`define S1(arg) "This is arg``s value %d", arg
`define S2(arg) `"This is arg``s value %d`", arg
module top;
parameter A=1 , B=2;
initial begin
  $display(`S1(A));
  $display(`S2(B));
end
endmodule

In the S2 macro, the `` is so that the processor sees arg as the name of the argument, not args. This displays:

This is arg``s value 1
This is Bs value 2