Why can't I pass the type wire as a parameter to an interface?

SystemVerilog
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1

I have a very simple parameterized interface, and I have been passing different types as parameters to it. Most types work fine, but I have been having trouble with wire.

Here is my code:

interface inf #(type T=logic);
  T val;
endinterface


module top();

  inf #(.T(wire)) d_inf();

endmodule

But when I run this, I get this syntax error:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "exp.sv", 3: token is 'wire'
    inf #(.T(wire)) d_inf();
                 ^

1 error

This works perfectly fine when I change the type from wire to logic or bit, so it’s clearly due to the type. But what is the problem here? I don’t see why wire wouldn’t be allowed as a parameterized type, and in fact if I create the same interface, non-parameterized, with type wire, it works fine! What’s going on here?

2

In reply to jms8:

Because a wire is not a data type. See Usage of Var | Verification Academy