Syntax error in a code block

UVM
, ,
1

I have the following code block where a syntax error is fired:


  virtual task body();
     forever begin
	my_transaction m_req;
	// Blocking wait for a transaction request:
	p_sequencer.m_request_fifo.get(m_req);
	// Generate response based on "req_kind" value:
	if ( m_req.req_kind == REQ ) begin
	   `uvm_do_with(req, {req_kind == REQ;} )
	end
	else begin
	   `uvm_do_with(req, {req_kind == NO_REQ;} )	   
	end
     end
  endtask

I get the following error message:


Error-[SE] Syntax error
  Following verilog source has syntax error :
  "./src/my_transaction.sv", 77: token is ')'
  	if ( m_req.req_kind == REQ ) begin
                                      ^

If I comment the if and else lines as follows, this code block compiles normally:


  virtual task body();
     forever begin
	my_transaction m_req;
	// Blocking wait for a transaction request:
	p_sequencer.m_request_fifo.get(m_req);
	// Generate response based on "req_kind" value:
	//if ( m_req.req_kind == REQ ) begin
	   `uvm_do_with(req, {req_kind == REQ;} )
	//end
	//else begin
	   `uvm_do_with(req, {req_kind == NO_REQ;} )	   
	//end
     end
  endtask

I tried commenting this line

my_transaction m_req;

as well and expected an error to fire up due to undefined

m_req

identifier. But the code actually compiles!

What can possibly be the issue?

2

In reply to khaledismail:

You are doing very specific things:

p_sequencer.m_request_fifo.get(m_req);

Which kind of code is this? The driver is performing the get.
Could you please show the declaration of req_kind?

3

In reply to chr_sue:

The definition of req_kind is:


class my_transaction extends uvm_sequence_item;
   typedef enum {REQ, NO_REQ} req_kind_e;
   rand req_kind_e req_kind;
...
...
...

and the class my_transaction is type forwarded in the file where the compilation error is present:

typedef class my_transaction;

The code block in question is a sequence in a sequence library where m_request_fifo is the port used in the slave sequencer to retrieve the sequence.

4

In reply to khaledismail:

Even with this information it is hard to give you an advice. But your approach should be re-archtiected.
Dealing with master/slave scenarios is shown in the code examples of the Verification Academy:
https://verificationacademy.com/cookbook/code-examples
Search for ‘Slave Agent Examples’.