Can I synthesis a top level module that has interfaces ? I’m confused because of the information I found in this link: systemVerilog - modelsim Altera starter - uses of interfaces · Issue #564 · cocotb/cocotb · GitHub
Here is an example
module top (
input clk,
input rst,
bus1_if.S bus1_if,
bus2_if.S bus2_if
);
<something>
endmodule
In reply to ghertz:
Strictly from a language point of view - No you cannot synthesize a top level design with a SystemVerilog Interface. As the error message in the reference link shows, an interface port of a module must be connected to an actual interface (there’s elaboration time checking happening between the port type and the connected interface).
An interface can only be instantiated at the calling module (or above). Since the synthesizer is only looking at module “top” there’s nothing above it to actually instantiate an interface.
From a practical point of view as well, the answer is NO as well. Most post-synthesis implementation tools, in practice, break down with anything other than than the most basic of port types at the top-level (think single-dimension vectors at most).
We use SystemVerilog Interfaces (and arrays thereof) heavily in our designs. But not at the top level.
Regards,
Mark
In reply to Mark Curry:
The concept of a top-level module may be different for simulation and synthesis tools. You’ll need to bring this up with your synthesis tool vendor. I do know that some tools provide a way to deal with this, but this Mentor sponsored public forum is not for discussion of tool specific issues.
@Mark @dave
Thank you! Switching back to basic ports for top level. I don’t think it’s a good idea to introduce confusion into the project by implementing something that only works sometimes
In reply to Mark Curry:
This leads to another question:
Isn’t it a lot of effort to map the top level IO signals to respective interface signals? For example:
module top (
input clk1,
input rst,
input bus1_in1,
input bus1_in2,
output bus1_out1,
output bus1_out2,
input bus2_in1,
input bus2_in2,
output bus2_out1,
output bus2_out2
);
//instantiate interfaces
bus1_if bus1_if_s() //bus1 interface slave
bus2_if bus2_if_s() //bus2 interface slave
//map interface signals – is there a better way to do this?
bus1_if_s.bus1_in1 = bus1_in1;
bus1_if_s.bus1_in2 = bus1_in2;
bus1_out1 = bus1_if_s.bus1_out1;
bus1_out2 = bus1_if_s.bus1_out2
//is there a better way to do this?
bus2_if_s.bus1_in1 = bus2_in1;
bus2_if_s.bus1_in2 = bus2_in2;
bus2_out1 = bus2_if_s.bus2_out1;
bus2_out2 = bus2_if_s.bus2_out2
mymodule1 mymodule1 (
.clk1(clk1),
.rst(rst),
.bus1_if_s(bus1_if_s)
);
mymodule2 mymodule2 (
.clk1(clk1),
.rst(rst),
.bus2_if_s(bus2_if_s)
);
endmodule
In reply to ghertz:
That’s pretty much what you need to do. Try and use vectors more, instead of single bit wires is the only suggestion I can offer.
Today’s top-level designs (both FPGAs and ASICs) can have 100s and even 1000s of signal I/Os. There’s going to be a bit of tedium to hook all these signals up in any solution.
Regards,
Mark
In reply to Mark Curry:
Alright. Thanks for the feedback.
Scripts are your friend.