In reply to ghertz:
That’s pretty much what you need to do. Try and use vectors more, instead of single bit wires is the only suggestion I can offer.
Today’s top-level designs (both FPGAs and ASICs) can have 100s and even 1000s of signal I/Os. There’s going to be a bit of tedium to hook all these signals up in any solution.
Regards,
Mark