In reply to Mark Curry:
This leads to another question:
Isn’t it a lot of effort to map the top level IO signals to respective interface signals? For example:
module top (
input clk1,
input rst,
input bus1_in1,
input bus1_in2,
output bus1_out1,
output bus1_out2,
input bus2_in1,
input bus2_in2,
output bus2_out1,
output bus2_out2
);
//instantiate interfaces
bus1_if bus1_if_s() //bus1 interface slave
bus2_if bus2_if_s() //bus2 interface slave
//map interface signals – is there a better way to do this?
bus1_if_s.bus1_in1 = bus1_in1;
bus1_if_s.bus1_in2 = bus1_in2;
bus1_out1 = bus1_if_s.bus1_out1;
bus1_out2 = bus1_if_s.bus1_out2
//is there a better way to do this?
bus2_if_s.bus1_in1 = bus2_in1;
bus2_if_s.bus1_in2 = bus2_in2;
bus2_out1 = bus2_if_s.bus2_out1;
bus2_out2 = bus2_if_s.bus2_out2
mymodule1 mymodule1 (
.clk1(clk1),
.rst(rst),
.bus1_if_s(bus1_if_s)
);
mymodule2 mymodule2 (
.clk1(clk1),
.rst(rst),
.bus2_if_s(bus2_if_s)
);
endmodule