In reply to ghertz:
Strictly from a language point of view - No you cannot synthesize a top level design with a SystemVerilog Interface. As the error message in the reference link shows, an interface port of a module must be connected to an actual interface (there’s elaboration time checking happening between the port type and the connected interface).
An interface can only be instantiated at the calling module (or above). Since the synthesizer is only looking at module “top” there’s nothing above it to actually instantiate an interface.
From a practical point of view as well, the answer is NO as well. Most post-synthesis implementation tools, in practice, break down with anything other than than the most basic of port types at the top-level (think single-dimension vectors at most).
We use SystemVerilog Interfaces (and arrays thereof) heavily in our designs. But not at the top level.
Regards,
Mark