Is there any way to store a reference to a variable?

SystemVerilog
, ,
1

I would like to be able to store a reference to a variable in a queue within a class so that I may modify the variable from the class later.

Here is what I have so far:


interface my_inf();

  logic value;
  logic ref_q[$];

  task register_value(ref logic x);
    ref_q.push_back(x);
  endtask
  
  task update_value();
    for (int i = 0; i < ref_q.size(); i++) begin
      ref_q[i] = value;
    end
  endtask

endinterface



module test();

  my_inf i();

  logic y, z;

  initial begin
    i.register_value(y);
    i.register_value(z);
    i.value = 0;
    i.update_value();  
    $display("y: %d, z:%d", y, z); // Should print y: 0, z: 0.
    i.value = 1;
    i.update_value();  
    $display("y: %d, z:%d", y, z); // Should print y: 1, z: 1.
  end
endmodule

Unfortunately, this code doesn’t work as intended. Is there any way to store a reference to an ordinary variable (logic, bit, int etc., not a class) in a class or interface and change the variables later? For example, is it possible to make a queue of references and pass it to the interface/ class? Or do I have to make the variable itself (y, z here) a class? I am looking for something like passing a pointer to a variable in C.

I have seen this question, which explains why the above code doesn’t work, but doesn’t suggest many possible solutions other than a class. I am hoping that is not the only solution to this problem.

2

In reply to jms8:
SystemVerilog does not have pointers to memory; it only has handles to dynamically allocated class objects. A class handle is an safe/opaque pointer with very limited operations that can be performed on it. What you can do is to wrap each variable in a class, and construct objects of that class whose handle can be passed around.

There may be other solutions, but I would need more details on the actual environment you are working with.