SV property - $fell

SystemVerilog
1 
property foo (clk_in, **stop**, baz, some_signal, fie, another_signal);
  @(posedge clk_in) disable iff (!AssertOn || !Resetn || some_signal || another_signal || !PwrOk || **stop**)
  $fell(**stop**) |=> ##8 $stable(baz) && ($past(fie,2) == 0);
endproperty

I want $fell(stop) to be a 1 to 0 transition and not an “x” to 0 transition.
How can I do this?
Thanks!

2

Use the $isunknown

! $isunknown(stop) && $fell(stop) |=>.. 
// stop              X. X. 0. 0. 1
// antecedent  0. 0. 0. 0. 1
3

Hi Ben,
Since the requirement is that there must be a 1 to 0 transition and not a “x” to 0 transition.
Shouldn’t we write it as

 !isunknown( $past(stop[0]) ) && $fell(stop) |=> ..

EDIT :: Changed from !isunknown( $past(stop) ) to !isunknown( $past(stop[0]) )