is $fell(sig_a) true when sig_a from x to 0?

SystemVerilog
,
2

$fell returns true if the lsb of the expression changes from 1/X/Z to 0

The same can be verified using

logic sig_a;

always@(posedge clk) begin
  if( $fell(sig_a) )
      $display("T:%0t $fell(sig_a) is true",$time);
  else
      $display("$T:%0t fell(sig_a) is false",$time);
end

// Add your stimulus as part of initial block

This would be true even when sig_a is sampled 0 on consecutive clocks

Using sv-property-fell the solution would be

!isunknown( $past(sig_a[0]) ) && $fell(sig_a)
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