Number of coverpoint bins

SystemVerilog
1

Hi,

bins x={[0:7],[8:15],[16:23],[24:31]}

I would expect 4 bins here with x[0] to x[3], but somehow I am getting 32 bins?

Is my understanding incorrect here?

2

Your understanding is incorrect.

The specification bins x[] = indicates that all the values on the right-hand side of the = should be distributed into up to 64 bins (64 being the implicit default). Since you have specified 32 values, you get 32 bins. Note that writing {{[0:7],[8:15],[16:23],[24:31]} is the same as writing {[0:31]}.

If you want to distribute the 32 values into 4 bins, with each bin containing 8 values, this can be achieved using the following code:

bins x[4] = {[0:31]};`
1 Like
3

Thanks Dave, I was following the coverpoint definition from below link. I guess they have specified it wrong then.

4

Hi Dave,

Wouldn’t the empty square brackets [] create one separate bin for each value on RHS ?
As per LRM ::

To create a separate bin for each value (an open array of bins), empty square brackets, [],shall follow the bin name. 

The following code example shows various bin groupings.
bit [9:0] v_a;
covergroup cg @(posedge clk);
coverpoint v_a
{
bins a = { [0:63],65 };
bins b[] = { [127:150],[148:191] }; // note overlapping values
bins c[] = { 200,201,202 };
bins d = { [1000:$] };
bins others[] = default;
}
endgroup
In this example, the first bins construct associates bin a with the values of variable v_a between 0 and 63
and the value 65. The second bins construct creates a set of 65 bins b[127] . . . b[191]. Note that when
empty square brackets are specified, each value is assigned one bin, including values that are specified more
than once.

As per my understanding the automatic bins ( 64 by default ) are created when user doesn’t specify bins explicitly

bit [9:0] s0;
covergroup g4;
coverpoint s0 iff(!reset); // 1024 values divided among 64 bins
endgroup

Please correct me if I am wrong