Possible alternative to multiple $test$plusargs

SystemVerilog
1

Hi All,
Consider the following code

initial begin
    if ( $test$plusargs ("ARG1") || $test$plusargs ("ARG2") || $test$plusargs ("ARG3") || $test$plusargs ("ARG4") || ... || $test$plusargs ("ARG10") )
     // Procedural code
   end
end

If there are numerous run-time args. that need to be checked, is there a possible solution similar to inside operator ?

initial begin
    <Some Logic here>
    if ( <Logic> inside { "ARG1" , "ARG2" , "ARG3" , "ARG4" .. , "ARG10" } )
     // Procedural code
   end
end
2

The UVM class uvm_cmdline_processor has a function get_arg_matches() that returns a queue of all the +args on the command line that match a regular expression. That expression could be a list of all the alternative switches you want to match.

I know that you’ve previously asked questions about UVM. However, even if your testbench isn’t based on UVM, you can utilize this class independently to achieve the functionality you’re looking for.

3

Thanks Dave. Tried an example for the same.
An interesting observation is if condition is true with run-time arg. as +ARG1232 for $test$plusargs whereas command line processor correctly identifies the difference